HV230/hv232 features hvcmos ? technology for high performance very low quiescent power dissipation C 10a output on-resistance typically 22 integrated bleed resistors on the outputs low parasitic capacitances dc to 10mhz analog signal frequency -60db typical output off isolation at 5.0mhz cmos logic circuitry for low power excellent noise immunity on-chip shift register, latch and clear logic circuitry flexible high voltage supplies applications medical ultrasound imaging piezoelectric transducer drivers ? ? ? ? ? ? ? ? ? ? ? ? ? block diagram low charge injection 8-channel high voltage analog switches with bleed resistors general description the supertex HV230 and hv232 are low charge injection 8- channel high-voltage analog switch integrated circuits(ics) with bleed resistors. these devices can be used in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. the bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. to reduce any possible clock feed-through noise, latch enable bar (le) should be left high until all bits are clocked in. using hvcmos technology, this switch combines high voltage bilateral dmos switches and low power cmos logic to provide ef? cient control of high voltage analog signals. these ics are suitable for various combinations of high voltage supplies, e.g., v pp /v nn : +50v/C150v, or +100v/C100v. le cl sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 v pp v nn v dd rgnd d out d in clk 8-bit shift register latches level shifters output switches d le cl d le cl d le cl d le cl d le cl d le cl d le cl d le cl
2 HV230/hv232 ordering information package options device 28-lead plcc 48-lead lqfp/tqfp (1.4mm) 26-lead bcc 26-ball fpbga HV230 - - - HV230ga HV230b1-g HV230ga-g hv232 hv232pj hv232fg -- hv232pj-g hv232fg-g -g indicates the part is rohs compliant (green) absolute maximum ratings parameter value v dd logic power supply voltage -0.5v to +15v v pp - v nn supply voltage 220v v pp positive high voltage supply -0.5v to v nn +200v v nn negative high voltage supply +0.5v to -200v logic input voltages -0.5v to v dd +0.3v analog signal range v nn to v pp peak analog signal current/channel 3.0a storage temperature -65 o c to +150 o c power dissipation: 28-lead plcc 48-lead lqfp/tqfp(1.4mm) 26-lead bcc 26-ball fpbga 1.2w 1.0w 1.0w 1.0w operating conditions symbol parameter value v dd logic power supply voltage 1,3 4.5v to 13.2v v pp positive high voltage supply 1,3 40v to v nn +200v v nn negative high voltage supply 1,3 -40v to -160v v ih high level input voltage v dd -1.5v to v dd v il low-level input voltage 0v to 1.5v v sig analog signal voltage peak-to-peak v nn +10v to v pp -10v 2 t a operating free air temperature 0 o c to 70 o c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. notes: 1. power up/down sequence is arbtrary except gnd must be powered -up ? rst and powered down last. 2. v sig must be v nn v sig v pp or ? oating during power up/down transition. 3. rise and fall times of power supplies v dd , v pp , and v nn should not be less than 1.0msec.
3 HV230/hv232 electrical characteristics dc characteristics (over recommended operating conditions unless otherwise noted) 30 26 38 48 i sig = 5ma v pp = 40v, 25 22 27 32 i sig = 200ma v nn = -160v small signal switch (on) r ons 25 22 27 30 ? i sig = 5ma v pp = 100v, resistance 18 18 24 27 i sig = 200ma v nn = -100v 23 20 25 30 i sig = 5ma v pp = 160v, 22 16 25 27 i sig = 200ma v nn = -40v small signal switch (on) ? r ons 20 5.0 20 20 % i sw = 5ma, v pp = 100v, resistance matching v nn = -100v large signal switch (on) r onl 15 ? v sig = v pp - 10v, i sig = 1a resistance output switch shunt r int 20 35 50 k ? output switch to r gnd resistance i rint = 0.5ma switch off leakage i sol 5.0 1.0 10 15 a v sig = v pp - 10v per switch dc offset switch off 300 100 300 300 mv no load dc offset switch on 500 100 500 500 mv no load pos. hv supply current i ppq 10 50 a all sws off neg. hv supply current i nnq -10 -50 a all sws off pos. hv supply current i ppq 10 50 a all sws on, i sw = 5ma neg. hv supply current i nnq -10 -50 a all sws on, i sw = 5ma switch output 3.0 3.0 2.0 2.0 a v sig duty cycle - 0.1% peak current output switch frequency f sw 50 khz duty cycle = 50% 6.5 7.0 8.0 v pp = 40v, v nn = -160v i pp supply current i pp 4.0 5.0 5.5 ma v pp = 100v, v nn = -100v 4.0 5.0 5.5 v pp = 160v, v nn = -40v 6.5 7.0 8.0 v pp = 40v, v nn = -160v i nn supply current i nn 4.0 5.0 5.5 ma v pp = 100v, v nn = -100v 4.0 5.0 5.5 v pp = 160v, v nn = -40v logic supply i dd 4.0 4.0 4.0 ma f clk = 5mhz, v dd = 5.0v average current logic supply i ddq 10 10 10 a quiescent current data out source current i sor 0.45 0.45 0.70 0.40 ma v out = v dd - 0.7v data out sink current i sink 0.45 0.45 0.70 0.40 ma v out = 0.7v logic input capacitance c in 10 10 10 pf 0c +25c +70c characteristics sym units test conditions min max min typ* max min max 50khz output switching frequency with no load *typical values only for hv232
4 HV230/hv232 electrical characteristics ac characteristics (over operating conditions v dd = 5v, unless otherwise noted) 0c +25c +70c characteristics sym min max min typ* max min max units test condi tions set up time before le rises t sd 150 150 150 ns time width of le t wle 150 150 150 ns clock delay time to data out t do 55 150 60 150 70 150 ns time width of cl t wcl 150 150 150 ns set up time data to clock t su 15 15 8.0 20 ns hold time data from clock t h 35 35 35 ns clock freq f clk 5.0 5.0 5.0 mhz 50% duty cycle f data = f clk /2 clock rise and fall times t r , t f 1.0 1.0 1.0 s turn on time t on 5.0 5.0 5.0 s v sig = v pp -10v, r l = 10k ? turn off time t off 5.0 5.0 5.0 s v sig = v pp -10v, r l = 10k ? 20 20 20 v pp = 160v, v nn = -40v maximum v sig slew rate dv/dt 20 20 20 v/ns v pp = 100v, v nn = -100v 20 20 20 v pp = 40v, v nn = -160v off isolation ko -30 -30 -33 -30 db f = 5mhz, 1k ? //15pf load -58 -58 -58 db f = 5mhz, 50 ? load switch crosstalk k cr -60 -60 -70 -60 db f = 5mhz, 50 ? load output switch isolation i id 300 300 300 ma 300ns pulse width, diode current 2.0% duty cycle off capacitance sw to gnd c sg(off) 5.0 17 5.0 12 17 5.0 17 pf 0v, 1mhz on capacitance sw to gnd c sg(on) 25 50 25 38 50 25 50 pf 0v, 1mhz ac characteristics (over operating conditions v dd = 5v, unless otherwise noted) v pp = 40v, v nn = -160v, r l = 50 ? v pp = 100v, v nn = -100v, r l = 50 ? v pp = 160v, v nn = -40v, r l = 50 ? 150 150 150 150 150 150 mv output voltage spike +25c units characteristics sym test conditions min typ* max +v spk -v spk +v spk -v spk +v spk -v spk *typical values only for hv232 electrical characteristics *typical values only for hv232
5 HV230/hv232 d0 d1 d2 d3 d4 d5 d6 d7 le cl sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 l l l off hllon l l l off hllon l l l off hllon llloff hllon l l l off hll on l l l off hll on lll off hll on l l l off hll on x x x x x x x x h l hold previous state x x x x x x x x x h off off off off off off off off truth table notes: 1. the eight switches operate independently. 2. serial data is clocked in on the l to h transition clk. 3. the switches go to a state retaining their present condition at the rising edge of le. when le is low the shift register data flows through the latch. 4. d out is high when data in shift register 7 is high. 5. shift register clocking has no effect on the switch states if le is h. 6. the clear input overrides all other inputs. data in clock data out d n + 1 n n - 1 d d 50% 50% 50% 50% 50% 50% 50% 50% 50% out (typ) v off on clr t wcl 90% 10% t off dd sd on t tt t t h wle su t le logic timing waveforms
6 HV230/hv232 test circuits switch off leakage i sol v pp 5v v nn v pp v nn v dd gnd v pp ?10v dc offset on/off v pp 5v v nn v pp v nn v dd gnd v out t on /t off test circuit v pp 5v v nn v pp v nn v dd gnd v pp ?10v r l 10k ? v out isolation diode current i id v pp 5v v nn v pp v nn v dd gnd v nn v sig crosstalk k cr = 20log v out v in v in = 10 v p ? p @5mhz nc 50 ? v pp 5v v nn v pp v nn v dd gnd 50 ? charge injection v pp 5v v nn v pp v nn v dd gnd v sig v out 1000pf q = 1000pf x ? v out ? v out output voltage spike v pp 5v v nn v pp v nn v dd gnd v out 1k ? r l 50 ? +v spk ?v spk off isolation k o = 20log v out v in v in = 10 v p ? p @5mhz v pp 5v v nn v pp v nn v dd gnd r l v out open r gnd r gnd open r gnd r gnd r gnd r gnd r gnd r gnd
7 HV230/hv232 pin function pin function 1 sw5 25 v nn 2 n/c 26 n/c 3sw427r gnd 4 n/c 28 gnd 5sw429v dd 6 n/c 30 n/c 7 n/c 31 n/c 8 sw3 32 n/c 9 n/c 33 d in 10 sw3 34 clk 11 n/c 35 le 12 sw2 36 clr 13 n/c 37 d out 14 sw2 38 n/c 15 n/c 39 sw7 16 sw1 40 n/c 17 n/c 41 sw7 18 sw1 42 n/c 19 n/c 43 sw6 20 sw0 44 n/c 21 n/c 45 sw6 22 sw0 46 n/c 23 n/c 47 sw5 24 v pp 48 n/c pin description pin description pin function pin function 1 sw3 15 n/c 2 sw3 16 d in 3 sw2 17 clk 4sw218 le 5sw119 cl 6 sw1 20 d out 7 sw0 21 sw7 8 sw0 22 sw7 9 n/c 23 sw6 10 v pp 24 sw6 11 r gnd 25 sw5 12 v nn 26 sw5 13 gnd 27 sw4 14 v dd 28 sw4 28-lead (j-lead) plcc package outline (pj) 48-lead lqfp/tqfp (1.4mm) package outline (fg) linear dimensions in millimeters. angular dimensions in degrees pin 1 identifier located within the area indicated corner shape may differ from drawing. . 0.22 0.05 0.50 bsc 9.00 0.20 7.00 0.20 9.00 0.20 7.00 0.20 1.60 max 0.45 - 0.75 0.05 - 0.15 0 o - 7 o 0.09 - 0.20 1.40 0.05 1.75 nom 1.75 nom 1 side view top view (4 places) 48 1 b. c. of bend radii 0.480 0.010 (12.192 0.254) 0.050 0.010 (1.270 0.254) 0.450 0.005 (11.430 0.127) 0.027 0.003 (0.6858 0.0762) 0.1725 0.0075 (4.3815 0.1905) min. 0.020 (0.508) 0.410 0.010 (10.414 0.254) 0.110 0.010 (2.794 0.254) dimensions in inches (dimensions in millimeters) measurement legend = 4 11 18 25
8 HV230/hv232 pin con? guration 26-ball fpbga package outline (ga) ball location function a4 sw1 c3 sw2 c4 sw1 c5 sw0 c6 v pp c7 v nn d1 sw3 d3 sw3 d4 sw2 d5 sw0 d6 r gnd d7 gnd d9 v dd e1 sw4 e3 sw4 e4 sw5 e5 sw7 e6 le e7 clk e9 d in f3 sw5 f4 sw6 f5 sw7 f6 d out f7 clr h4 sw6 top view bottom view enlarged side view 0.800.05 1.00.10 0.200.05 0.330.05 0.65 0.65 1.70 1.70 2.68 5.350.10 6.000.10 a1 indicator 3.00 a1 indicator note: all dimensions are in millimeters
9 doc.# dsfp-HV230_hv232 a111006 HV230/hv232 (the package drawing(s) in this data sheet may not re? ect the most current speci? cations. for the latest package outline information go to http://www.supertex.com/packaging.html .) pin description pin function 1 sw4 2sw3 3sw3 4sw2 5sw2 6sw1 7sw1 8sw0 9sw0 10 v pp 11 v nn 12 r gnd 13 gnd 14 v dd 15 d in 16 clk 17 le 18 clr 19 d out 20 sw7 21 sw7 22 sw6 23 sw6 24 sw5 25 sw5 26 sw4 26-lead bcc package outline (b1) HV230b1 package outline top view pad connections are on the backside of the package. pin 1 pin 2 10 18 4.15 6.000. 0.925 0.925 4.55 0.389 0.350.10 1.06 0.725 0.65 0.725 0.350.10 0.40 1.05 6.000.10 0.8mm max 0.0750.025 (standoff ) side view 0.10
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